1. Field of the Invention
The present invention relates to a semiconductor capacitive element, a method for manufacturing the same and a semiconductor device provided with the same, and more particularly to the semiconductor capacitive element using buried wirings formed in an interlayer dielectric on a semiconductor substrate as electrodes, the method for manufacturing the semiconductor capacitive element and the semiconductor device provided with the semiconductor capacitive element.
The present application claims priority of Japanese Patent Application No. 2002-127639 filed on Apr. 26, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
In a semiconductor device typified by an LSI (Large Scale Integrated circuit), due to a change in a potential of a power source caused by reversing of a logical value occurring at a time of switching operations, a power source noise occurs. Such the power source noise affects a normal operation of the semiconductor device, causing a malfunction. Therefore, in order to reduce the power source noise, a semiconductor capacitive element (hereinafter may be referred to as a semiconductor capacitor) serving as a decoupling capacitor or a by-pass capacitor is generally formed and embedded in the semiconductor device.
On the other hand, as an integration degree of a recently-available LSI is heightened, dimensions of each semiconductor device are made more smaller and, as a result, dimensions of a semiconductor region making up each semiconductor device are also becoming smaller. When wirings being connected in such a small region of the semiconductor device are formed, since high wiring density corresponding to such the high integration degree cannot be obtained merely by forming wirings in a plane direction on a semiconductor substrate, multi-layer wiring technology is employed in which wirings are formed through multi-layers in a direction of a thickness on the semiconductor substrate.
Moreover, in such the LSIs as described above, since an operation speed of the semiconductor device is greatly influenced by a resistance of a wiring, it is desirable that the wiring having a low resistance is formed. From this viewpoint, in recent years, as a material for the wiring, instead of Al (aluminum) or Al metals containing Al as a chief ingredient, Cu (Copper) or Cu metals containing Cu as a chief ingredient, which has a resistance being lower than that of the Al or Al metals, tend to be widely used. However, when the wiring is formed by using Cu metals as its material, since a vapor pressure of a Cu compound is low, unlike in the case of using the Al metals, it is difficult to perform patterning on a Cu-based wiring so as to obtain a desired shape by using dry-etching technology. Therefore, to form the wiring having a desired shape by using Cu metals, so-called Damascene wiring method is employed in which a wiring trench is formed in an interlayer dielectric formed on the semiconductor substrate and a buried wiring is formed in the wiring trench. That is, in the Damascene wiring method, after Cu metals have been formed on entire surfaces of the interlayer dielectric including the wiring trench, unwanted Cu metal films formed on the interlayer dielectric are removed by using a CMP (Chemical Mechanical Polishing) method and the Cu metal film being left (buried) only in the wiring trench is used as the wiring. Moreover, a Dual Damascene wiring structure, as described later, obtained by further development of the Damascene wiring structure (hereinafter single Damascene wiring structure) is employed as a structure being suitable to multi-layer wiring technology in particular.
That is, according to the dual Damascene wiring method, after a via interlayer dielectric and an upper interlayer dielectric have been sequentially formed on the semiconductor substrate on which a lower layer wiring had been formed in advance, a via hole and an upper layer wiring trench are formed on each of the via interlayer dielectric and the upper interlayer dielectric, and then after Cu-metal films have been formed on entire surfaces of them, unwanted Cu-metal films are removed by using the CMP method in a manner that the Cu-metal films are left only within the via hole and the upper layer wiring trench to construct both a via plug and an upper layer wiring. Thus, a dual Damascene wiring structure is obtained in which the lower layer wiring is electrically connected to the upper layer wiring through the via plug. As described above, the dual Damascene wiring structure is superior to the single Damascene structure described above from viewpoints of cost reduction and high TAT (Turn-Around-Time) of LSIs achieved by simultaneous formation of the via plug and the upper layer wiring thereby enabling a decrease in a number of manufacturing processes. The larger the number of wiring layers, the higher its effects.
By using such the Damascene wiring method or the dual Damascene wiring method, a semiconductor capacitor serving as a decoupling capacitor as described above is generally embedded into the semiconductor device. For example, in Japanese Patent Application Laid-open No. 2000-228497, a semiconductor capacitor and its manufacturing method using the dual Damascene wiring method described above are disclosed. A semiconductor capacitor 120, as shown in FIG. 11, is so constructed that, on a substrate 100 on which lower components such as transistors (not shown) are formed, a first interlayer dielectric 102, a first etching stopper film (also called a cap film) 104, a second interlayer dielectric 106, a third interlayer dielectric 110, a second etching stopper film 112, and a fourth interlayer dielectric 114 are sequentially formed and that a lower electrode 108b is formed in such a manner as to be buried in the second interlayer dielectric 106 and that a dielectric film (capacity interlayer dielectric) 116 and an upper electrode 118b are formed in such a manner as to be sequentially buried in a first via hole h2 formed on the second etching stopper film 12 and the third interlayer dielectric 110.
Next, a method for manufacturing the conventional semiconductor capacitor is described in order of processes by referring to FIGS. 12A-12E.
First, as shown in FIG. 12A, the first interlayer dielectric 102 is formed on a substrate 100 on which lower components such as transistors (not shown) are formed. After the first etching stopper film 104 and the second interlayer dielectric 106 have been sequentially formed on the first interlayer dielectric 102, by using a photosensitive photo-resist film (not shown) as a mask, the second interlayer dielectric 106 in a region corresponding to a multi-layer wiring forming portion 103 and in a region corresponding to a capacitor forming portion 105 is etched until a surface of the first etching stopper film 104 is exposed. Then, a part of the first etching stopper film 104 corresponding to the multi-layer wiring forming portion 103 and a part of the first interlayer dielectric 102 also corresponding to the multi-layer wiring forming portion 103 are etched until a surface of the substrate 100 is exposed to form a contact hole h1.
Next, as shown in FIG. 12B, after Cu-films have been formed on all surfaces of the second interlayer dielectric 106 and first etching stopper film 104 including the contact hole hi, by using the CMP method, the Cu-films are removed until the second interlayer dielectric 106 is exposed and then a first wiring line 108a is formed in a manner that the Cu-films are buried in a region corresponding to the multi-layer wiring forming portion 103 and, at a same time, a lower electrode 108b is formed in a manner that the Cu-films are buried in a region corresponding to the capacitor forming portion 105. Next, as shown in FIG. 12C, after the third interlayer dielectric 110, the second etching stopper film 112, and the fourth interlayer dielectric 114 have been sequentially formed on all surfaces of the second interlayer dielectric 106, the first wiring line 108a, and the lower electrode 108b, by using a photosensitive photo-resist film (not shown), the fourth interlayer dielectric 114 of a part corresponding to the multi-layer wiring forming portion 103 and of apart corresponding to the capacitor forming portion 105 is etched until a surface of the second etching stopper film 112 is exposed.
Then, as shown in FIG. 12D, by using a photosensitive film (not shown) as a mask, after the second etching stopper film 112 and the third interlayer dielectric 110 of a region corresponding to the capacitor forming portion 105 are etched until the lower electrode 108b is exposed to form a first via hole h2, a dielectric film 116 is formed on all surfaces of the fourth interlayer dielectric 114, the second etching stopper film 112, and the third interlayer dielectric 110 including the first via hole h2. Next, the dielectric film 116, the second etching stopper film 112, the third interlayer dielectric 110 of a region corresponding to the multi-layer wiring forming portion 103 are etched until a surface of the first wiring line 108a is exposed to form a second via hole h3. Then, as shown in FIG. 12E, after a Cu-film has been formed on all surfaces of the dielectric film 116, the second etching stopper film 112, the third interlayer dielectric 110 including the first via hole h2 and second via hole h3, by using the CMP method, the Cu-film is removed until the dielectric film 116 is exposed to form a second wiring line 118a in a manner that the Cu film is buried in a region corresponding to the multi-layer wiring forming portion 103 and, at a same time, to form the upper electrode 118b in a manner that the Cu film is buried in a region corresponding to the capacitor forming portion 105.
Thus, the semiconductor device 121 is manufactured by integrating a multilayer wiring 119 obtained by connecting the first wiring line 108a with the second wiring line 118a in the region corresponding to the multi-wiring forming portion 103 and a semiconductor capacitor 120 obtained by having the dielectric film 116 be interposed between the lower electrode 108b and the upper electrode 118b in the region corresponding to the capacitor forming portion 105 as shown in FIG. 11. It is, therefore, possible to make the semiconductor capacitor 120 operate as a decoupling capacitor in the semiconductor device 121.
However, the semiconductor capacitor 120 has a problem in that its parasitic capacity is large and the conventional method for manufacturing the semiconductor capacity also has a problem in that a large number of processes is required for manufacturing. That is, in the semiconductor capacitor 120 shown in FIG. 11, the dielectric film 116 extends not only to a portion facing the lower electrode 108b but also to side faces of the third interlayer dielectric 110 and the fourth interlayer dielectric 114 within the first via hole h2 and further a dielectric constant of the dielectric film 116 is larger than those of the third and fourth interlayer dielectrics 110 and 114. As a result, the dielectric film 116 formed on portions other than that facing the lower electrode 108b causes parasitic capacity to become large. Therefore, in a semiconductor device aiming at achieving high-speed operations in particular, its operational speed is affected by the existence of parasitic capacity. Moreover, in the conventional method of manufacturing the semiconductor capacitor 120 described above, as shown in FIG. 12D, a film forming process to form the dielectric film 116 is needed, which causes an increase in the number of manufacturing processes and in costs.
To solve this problem, in the case of a semiconductor capacitor and its manufacturing method by using the Dual Damascene wiring method described above, the semiconductor capacitor and its manufacturing method to suppress an occurrence of parasitic capacity are disclosed, for example, in Japanese Patent Application Laid-open No. 2001-274328. The disclosed semiconductor capacitor 148, as shown in FIG. 13, has a lower layer wiring 133 formed on a first interlayer dielectric 131 with an etching stopper film 132 being interposed between the first interlayer dielectric 131 and the lower layer wiring 133, a capacitive insulating film 134 formed within a second interlayer dielectric 139, and an upper electrode 137 also formed within the second interlayer dielectric 139 in which the upper electrode 137 is connected through via plugs 146 formed within the second interlayer dielectric 139 to an upper layer wiring 147 formed in an etching stopper film 140 and in a third interlayer dielectric 141. In the semiconductor capacitor 148, since the capacitive insulating film 134 is formed only on the lower layer wiring 133 serving as a lower electrode, the occurrence of parasitic capacity as described above can be suppressed.
Next, the method for manufacturing the semiconductor capacitor is described in order of processes by referring to FIGS. 14A to 14G. First, as shown in FIG. 14A, after an etching stopper film 132 and another interlayer dielectric (not shown) have been sequentially formed on a first interlayer dielectric 131, as shown in FIG. 14B, by using the Damascene wiring process, the lower layer wiring 133 is formed in a manner that a film made of a metal such as Cu is buried in a wiring trench (not shown) formed in the another interlayer dielectric (not shown). Next, as shown in FIG. 14C, after the capacitive insulating film 134 and an electrode material film 135 have been formed on the lower layer wiring 133, an unwanted portion of the electrode material film 135 is etched by using a photo-resist film 136 as a mask, the upper electrode 137 is formed as shown in FIG. 14D. Next, the second interlayer dielectric 139, the etching stopper film 140, and the third interlayer dielectric 141 are sequentially formed.
Then, as shown in FIG. 14E, the third interlayer dielectric 141, the etching stopper film 140, the second interlayer dielectric 139 are etched until the upper electrode 137 is exposed to form a via hole 142. Next, as shown in FIG. 14F, the third interlayer dielectric 141 and the etching stopper film 140 are etched until the second interlayer dielectric 139 is exposed to form a wiring trench 143 and, at a same time, until the via hole 142 is exposed to form a wiring trench 144. Then, as shown in FIG. 14G, a metal film 145 such as a Cu film is formed on all surfaces of the third interlayer dielectric 141, and the etching stopper film 140, and the second interlayer dielectric 139 including the wiring trenches 143 and 144. Next, by removing the metal film 145 until the third interlayer dielectric 141 is exposed using the CMP method, the metal film 145 is buried into the via hole 142 to form the via plugs 146 and, at a same time, by burying the metal film 145 into the wiring trenches 143 and 144 to manufacture a semiconductor capacitor 148 as shown in FIG. 13. Therefore, it is possible to have the semiconductor capacitor 148 operate as a decoupling capacitor.
In the semiconductor capacitor 148 and its manufacturing method disclosed in Japanese Patent Application Laid-open No. 2001-274328, though the occurrence of parasitic capacity in the semiconductor capacity can be suppressed, there still exists a problem of an increase in the number of manufacturing processes. That is, even in the method of manufacturing the semiconductor capacitor 148 disclosed in Japanese Patent Application Laid-open No. 2001-274328, as shown in FIG. 14C, since the film forming process to form the capacitive insulating film 134 is needed, like in the case of the manufacturing method disclosed in Japanese Patent Application Laid-open No. 2000-228497, the number of manufacturing processes increases and therefore increases in costs are unavoidable.